Builds
Things I've made.
From a pipelined CPU to trust infrastructure securing GPU workloads: the projects I've built, broken, and rebuilt.
March – May 2025
RISC-V CPU in Verilog & Logisim
A 3-stage pipelined RISC-V CPU, prototyped from scratch and verified like production hardware.
- Designed a 3-stage pipelined RISC-V datapath (Fetch, Decode/Execute, Memory/Writeback) with a full register file and PC control logic, prototyped in Logisim.
- Wrote SystemVerilog assertions and directed testbenches to formally check datapath, register file, and PC-update correctness cycle by cycle.
- Used waveform-based debugging to isolate and fix faulty PC updates, misaligned instruction fetches, and memory-timing bugs across the pipeline.
Summer 2025 · Nutanix
GPU & Host Trust Attestation Infrastructure
End-to-end trust infrastructure securing confidential AI/ML workloads across physical hosts and GPUs.
- Implemented TPM 2.0 remote attestation using PCR-based measured boot and cryptographic verification, enabling secure access control for AHV hosts and NVIDIA H100 GPUs.
- Deployed end-to-end attestation infrastructure integrating cloud flows (AMD SEV-SNP, NVIDIA Trust Outpost) with per-session secrets locked behind AIK credential activation and PCR validation.
Summer 2025 · Citylitics
18M+ URL Data Integration Pipeline
Automated extraction and curation pipeline that turned a noisy web crawl into a gold-standard ML dataset.
- Built an automated extraction pipeline from an 18M+ URL web crawl into BigQuery, cutting noise by ~70% and halving query runtime.
- Designed a human-in-the-loop labeling workflow with anomaly detection to catch mislabeled and out-of-distribution records.
- Delivered a gold-standard curated dataset that accelerated downstream ML dataset preparation across the team.
Student project
Formula Electric Battery Management System
Battery management system work for a Formula Electric racing team.
- Designed KiCad schematics for pack-level battery temperature sensing, per-cell voltage sensing, and transistor-switched cell balancing.
- Built voltage-sensing circuitry around LMV331 comparators feeding the MCU's ADC inputs for real-time cell monitoring.
- Mapped the MCU pinout and embedded C interfacing between the sensing hardware and the accumulator EE stack for the team's electric race vehicle.
Student project
Two-Stage Op-Amp
Analog circuit design and simulation of a two-stage operational amplifier.
- Designed a two-stage op-amp: a telescopic cascode first stage for high gain and a class AB second stage for low quiescent current, linked by a Miller compensation cap.
- Sized transistors and a 7.25:1 current-mirror bias to hit a closed-loop gain of 2 while meeting a 180ns settling-time spec.
- Simulated 65.4° phase margin, 0.044% total error, and 138.3ns settling time at 801.6µW, beating the target static and dynamic error budgets.
Student project
SIXT33N: Voice-Controlled Car
A voice-controlled car built for an embedded systems design course.
- Characterized motor dynamics via a PWM duty-cycle sweep and encoder logging, fitting per-wheel linear velocity models (θ, β) to correct for wheel asymmetry.
- Built closed-loop control on wheel-distance differential (δ[i] = d_L[i] − d_R[i]) for straight-line driving and controlled 90° turns, with startup jolts to overcome static friction.
- Trained a PCA/SVD voice classifier (3 principal components, ~40 samples per word) to recognize 4 spoken commands and trigger the matching drive maneuver in real time.
Final demo: SIXT33N listening for a voice command and driving the corresponding maneuver.